1. Field of the Invention
The present invention relates to a semiconductor device including a transistor and a capacitor formed on the major surface of a semiconductor substrate, a semiconductor integrated circuit device formed by integrating such semiconductor devices, and a method of manufacturing same.
2. Description of the Related Art
In an integrated circuit formed by integrating memory cells including Metal Oxide Semiconductor (MOS) transistors and capacitors on the major surface of a semiconductor substrate, the integration density can be increased by reducing an area occupied by the capacitors on the major surface of the semiconductor device, so that a large-scale integrated circuit can be realized.
As a capacitor used such a memory cell, a stacked capacitor formed to extend upward from the major surface of a semiconductor substrate, or a trench capacitor formed by forming a trench in the major surface is known. In a memory cell using such a capacitor, a unit memory cell is generally constituted as a one-transistor memory cell including one MOS transistor and one capacitor.
According to the one-transistor memory cell, since the number of functional circuit elements constituting a unit memory cell is small, an area occupied by the unit memory cell is small. For this reason, the number of memory cells per a unit area, i.e., an integration density in a storage element integrated device can be sufficiently increased.
However, in recent years, a power supply voltage tends to decrease with development of micropatterning technique, thereby compressing a signal amplitude. An operation of reliably reading an information signal from a memory cell cannot be easily performed.
For example, in a dynamic random access memory (DRAM), a signal from a memory cell at a read address is transmitted to one of a pair of bit lines, and the other of the pair of bit lines receives a signal from a dummy cell, so that a potential difference between the pair of bit lines is detected as information by using a gated flip-flop as a sensing circuit.
In this sensing operation, in a storage circuit using the one-transistor memory cell, an amount of a setting error of a signal potential of the dummy cell or an amount of a variation in power supply voltage is a part which cannot be used as a dead zone of the power supply potential. For this reason, when the power supply voltage is lowered with development of micropatterning technique, a stable storing operation cannot be performed.
In order to avoid this problem, for example, as described in Japanese Patent Application No. 59-136110 (Japanese Patent Application Laid-Open No. 61-16099), Japanese Patent Application No. 60-81829 (Japanese Patent Application Laid-Open No. 61-240497), Japanese Patent Application No. 60-204087 (Japanese Patent Application Laid-Open No. 62-65295), a two-transistor memory cell structure in which one memory cell includes two transistors and one capacitor to complementarily transmit the same information signal to both of a pair of bit lines is proposed.
However, in the two-transistor memory cell constituted by two MOS transistors and one capacitor, a space occupied by each memory cell increases. For this reason, the two-transistor memory cell structure cannot be easily realized without decreasing an integration density, i.e., a memorizing density. Therefore, an increase in integration density of storage elements and a stable operation performed under the state wherein the power supply voltage is lowered with application of micropatterning technique can not be made compatible.